1. Field of the Invention
The present invention relates to a jitter detection circuit of a phase locked loop circuit (PLL circuit).
2. Description of the Related Art
A PLL circuit is integrated in a variety of devices, systems, and so forth and is employed in order to generate clocks for same. In Japanese Unexamined Patent Publication No. 2001-346127, a PLL circuit is integrated in a circuit that converts the aspect ratio of a picture signal and generates a sampling clock.
A jitter component is normally contained in a clock generated by a PLL circuit. When the jitter component exceeds a permissible value, it impedes normal operation of the device, system or the like in which the PLL circuit is integrated. Therefore, a circuit which detects the magnitude of the jitter contained in the clock generated by the PLL circuit exceeds the permissible value and outputs the detection result is very useful.
One example of the jitter detection circuit is shown in FIG. 11, for example, though the circuit does not constitute the Prior Art. In the jitter detection circuit, the phase difference between the input clock and the output clock is smoothed by a low pass filter (LPF) 110. The phase difference, which is analog value, is compared by using an analog comparator 120. Thus, the jitter detection circuit detects that the jitter contained in the output clock exceeds the permissible value. Specifically, the PLL circuit 100 comprises a phase comparator 102, LPF 104, a voltage controlled oscillator (VCO) 106 and divider 108. The output of the phase comparator 102 is inputted to an LPF 110.
However, the circuit in FIG. 11 is not capable of measuring the phase difference accurately and there is therefore the problem that the jitter detection accuracy is low. That is, an error occurs in the output of the phase comparator 102 and the threshold value voltage of the analog comparator 120 due to fluctuation in manufacture. This impedes achieving high accuracy in the jitter detection.